Chip marketing is a fog of petaflops. Here is how to read a spec sheet like the ones in our chip database — and which numbers to trust.
FLOPS come with a precision label
A floating-point operation can use 64 bits of precision or 4. Halve the bits and you roughly double the speed, so the same chip lists wildly different numbers: an H100 does 34 TFLOPS at FP64 but nearly 2,000 TFLOPS ("2 petaflops") at FP8. AI tolerates low precision surprisingly well — weights at 8 or even 4 bits still work — which is why each hardware generation adds a lower format: FP8 in Hopper, FP4 in Blackwell. When comparing chips, compare the same precision.
Watch for the sparsity asterisk
NVIDIA headline figures usually assume "structured sparsity" — half the values are zero and skipped — which doubles the quoted number. Real workloads rarely qualify fully. This site lists dense figures and notes sparsity separately; when a vendor slide says 20 PFLOPS and our record says 9–10, that is the difference you are seeing.
Memory is usually the real spec
Two numbers dominate real performance: memory capacity (can the model fit close to the compute?) and memory bandwidth (how fast can weights stream in?). Generating each token requires touching essentially all active weights, so tokens per second track bandwidth almost linearly. This is why the H200 — identical compute to H100, 76% more memory, 43% more bandwidth — served large models nearly twice as fast, and why HBM supply decides product roadmaps.
TDP and the system tax
Thermal design power is the chip's budgeted draw: 700 W for an H100 SXM, up to 1,400 W for a MI355X. Roughly double per-GPU power to estimate the full server share (CPUs, networking, fans, power-conversion losses), then add ~10–30% facility overhead (PUE). A 1,000 W GPU is really a ~2 kW commitment at the meter.
Interconnect: the number that makes clusters
Per-chip specs stop mattering the moment models span chips. Scale-up bandwidth (NVLink: 900 GB/s on Hopper, 1.8 TB/s on Blackwell) sets how well 8–72 GPUs pool memory; scale-out networking (InfiniBand/Ethernet, 400–800 Gb/s per GPU) sets cluster efficiency. A mediocre chip with a great fabric often beats the reverse.
The honest hierarchy
For training: interconnect, then memory bandwidth, then dense BF16/FP8 FLOPS. For inference: memory capacity and bandwidth, then FP8/FP4 throughput, then cost per token. For everything: MLPerf results beat datasheets — measured beats claimed.
