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Chip
Google TPU v1–v3
The originals: the 2015 inference ASIC that started the custom-silicon era.
TPU v1 (deployed 2015, revealed 2016) was a 28 nm inference ASIC built in 15 months after Google calculated that voice search at scale would otherwise require doubling its data centers. v2 (2017) added training, HBM and the first pods; v3 (2018) went liquid-cooled at 1,024-chip scale and trained early BERT-era models. Together they proved a hyperscaler…
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