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Home › Chips › Google TPU v7 (Ironwood)

Google TPU v7 (Ironwood)

Chip AI Accelerator Ramping

Google's inference-age flagship: 4.6 PFLOPS FP8 and 9,216-chip superpods.

You're looking at a chip record: what this processor is, its key specs, who designs, manufactures and supplies its parts, and where it gets used.

Ironwood, announced April 2025 and generally available late 2025, is Google's first TPU pitched for the 'age of inference': 4,614 TFLOPS of FP8 per chip, 192 GB of HBM3E at 7.4 TB/s, and pods scaling to 9,216 liquid-cooled chips. Anthropic's October 2025 agreement to access up to one million TPUs — reported at up to a gigawatt of capacity in 2026 — made it the largest publicly known TPU commitment.

Specifications & key facts

Each figure is labeled by basis: vendor spec, vendor claim, reported, estimate, or official. "Not publicly disclosed" means exactly that — we never invent values.

Overview

Designer Google
Announced April 2025; GA late 2025
Status Ramping

Memory

Memory 192 GB HBM3EVendor spec
Memory bandwidth 7.37 TB/sVendor spec

Compute

FP8 4,614 TFLOPSVendor spec

Physical

Pod scale 9,216 chips (superpod); ~42.5 FP8 ExaFLOPS per podVendor claim
Cooling Direct liquid coolingVendor spec

How this connects to the rest of the stack

This record's links at a glance — click a group to jump to it. +2 more groups below.

Designed by

Memory technology

Found inside

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Competes with

Sources

Ironwood announcement ↗

Record reviewed as of 2026-01-15 — see Methodology.