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Google TPU v1–v3

芯片 AI加速器历史

The originals: the 2015 inference ASIC that started the custom-silicon era.

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照片: Zinskauf · CC BY-SA 4.0 · Wikimedia Commons

TPU v1 (deployed 2015, revealed 2016) was a 28 nm inference ASIC built in 15 months after Google calculated that voice search at scale would otherwise require doubling its data centers. v2 (2017) added training, HBM and the first pods; v3 (2018) went liquid-cooled at 1,024-chip scale and trained early BERT-era models. Together they proved a hyperscaler could out-build the merchant market for its own workloads — the argument every custom AI chip since has followed. AlphaGo ran on TPUs when it beat Lee Sedol in 2016.

规格与关键参数

每个数据均标注来源依据：厂商规格、厂商声明、公开报道、估算或官方数据。"未公开披露"即字面含义——我们从不捏造数值。

Overview

Designer Google

Deployed v1 2015 · v2 2017 · v3 2018

Legacy Introduced BF16 to hardware and the pod-scale systems model

算力

TPU v1 92 TOPS INT8, inference onlyPublished paper

TPU v2 45 TFLOPS BF16 per chip; first 256-chip podsVendor spec

TPU v3 123 TFLOPS BF16 per chip; liquid-cooled 1,024-chip podsVendor spec

它如何与整个技术栈相连

本记录的关联链接一览——点击分组可直接跳转。

设计方

Google (Alphabet)

用于训练

AlphaGo / AlphaZero

后继产品

Google TPU v4

来源

TPU v1 paper (ISCA 2017) ↗

记录审阅截至 2026-01-15 — 查看方法论.