Google TPU v1–v3
The originals: the 2015 inference ASIC that started the custom-silicon era.
You're looking at a chip record: what this processor is, its key specs, who designs, manufactures and supplies its parts, and where it gets used.
Photo: Zinskauf · CC BY-SA 4.0 · Wikimedia Commons
TPU v1 (deployed 2015, revealed 2016) was a 28 nm inference ASIC built in 15 months after Google calculated that voice search at scale would otherwise require doubling its data centers. v2 (2017) added training, HBM and the first pods; v3 (2018) went liquid-cooled at 1,024-chip scale and trained early BERT-era models. Together they proved a hyperscaler could out-build the merchant market for its own workloads — the argument every custom AI chip since has followed. AlphaGo ran on TPUs when it beat Lee Sedol in 2016.
Specifications & key facts
Each figure is labeled by basis: vendor spec, vendor claim, reported, estimate, or official. "Not publicly disclosed" means exactly that — we never invent values.
Overview
Compute
How this connects to the rest of the stack
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Designed by
Used to train
Succeeded by
Sources
Record reviewed as of 2026-01-15 — see Methodology.