{"data":{"slug":"google-tpu-v4","etype":"chip","name":"Google TPU v4","cat":"AI Accelerator","subtitle":"The TPU generation that proved optical circuit switching at 4,096-chip scale.","summary":"TPU v4 pods connected 4,096 chips through reconfigurable optical circuit switches — Google's bet that the network, not the chip, defines a training machine. PaLM was trained across two v4 pods. Its published 275 BF16 TFLOPS per chip trailed contemporary GPUs, but pod-scale efficiency was the point.","attrs":[{"g":"Overview","l":"Designer","v":"Google"},{"g":"Overview","l":"Family","v":"Tensor Processing Unit"},{"g":"Overview","l":"Deployed","v":"2020; described publicly 2021–2023"},{"b":"Vendor spec","g":"Memory","l":"Memory","v":"32 GB HBM2"},{"b":"Vendor spec","g":"Memory","l":"Memory bandwidth","u":"TB/s","v":"1.2"},{"b":"Vendor spec","g":"Compute","l":"BF16","u":"TFLOPS","v":"275"},{"b":"Vendor spec","g":"Compute","l":"INT8","u":"TOPS","v":"275"},{"b":"Published paper","g":"Power","l":"Typical chip power","v":"~192 W (paper figure)"},{"b":"Published paper","g":"Physical","l":"Pod scale","v":"4,096 chips via optical circuit switching"}],"kf":{"node":"TSMC N7","year":2021,"class":"AI Accelerator","tdp_w":192,"mem_bw":1.2,"memory":"32 GB HBM2","designer":"Google"},"aliases":["TPU v4","TPUv4"],"ticker":null,"exchange":null,"hq":null,"founded":null,"website":null,"status":"Prior generation","region":null,"asof":"2026-01-15","sources":[{"url":"https://arxiv.org/abs/2304.01433","label":"TPU v4 paper (ISCA 2023)"}]},"meta":{"found":true,"count":1,"served_from":"site cache (no live upstream calls)","as_of":"2026-10-14T03:49:42+00:00","disclaimer":"Research and information only — not investment advice. Structured records carry basis labels (vendor spec / reported / estimate); market quotes are delayed/indicative.","attribution":"Records compiled from vendor documentation, official filings and reputable public reporting; market quotes via financial data providers. See /data-sources."}}