{"data":{"slug":"cowos","etype":"tech","name":"CoWoS","cat":"Packaging","subtitle":"TSMC's 2.5D packaging — the assembly step that rationed the world's GPUs.","summary":"Chip-on-Wafer-on-Substrate mounts GPU dies and HBM stacks side by side on a silicon interposer. Every NVIDIA and AMD flagship uses it, and during 2023–24 CoWoS capacity — not wafer supply — was the binding constraint on global GPU output, forcing TSMC to multiply capacity several-fold. CoWoS-L, with local silicon bridges in an organic interposer, carries Blackwell and Rubin's ever-larger assemblies.","attrs":null,"kf":null,"aliases":["CoWoS-S","CoWoS-L","chip on wafer on substrate"],"ticker":null,"exchange":null,"hq":null,"founded":null,"website":null,"status":null,"region":null,"asof":"2026-01-15","sources":[{"url":"https://3dfabric.tsmc.com/","label":"TSMC 3DFabric"}]},"meta":{"found":true,"count":1,"served_from":"site cache (no live upstream calls)","as_of":"2026-10-14T06:50:51+00:00","disclaimer":"Research and information only — not investment advice. Structured records carry basis labels (vendor spec / reported / estimate); market quotes are delayed/indicative.","attribution":"Records compiled from vendor documentation, official filings and reputable public reporting; market quotes via financial data providers. See /data-sources."}}